AS4C1G16MD4V-046BIN

Name: Alliance Memory AS4C1G16MD4V-046BIN
Brand: Alliance Memory
SKU: 913-4C1G16MD4V046BIN
Price: 203.25 EUR
Availability: OutOfStock

Mouser No:

913-4C1G16MD4V046BIN

Mfr. No:

AS4C1G16MD4V-046BIN

Mfr.:

Alliance Memory

Description:

DRAM LPDDR4X, 16Gb, 1G X 16, 0.6V, 200ball TFBGA, 2133mhz, INDUSTRIAL TEMP

Lifecycle:

End of Life:

Scheduled for obsolescence and will be discontinued by the manufacturer.

Datasheet:

AS4C1G16MD4V-046BIN Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about Alliance Memory AS4C1G16MD4V-046BIN

.hidden-for-nojs { display: none; } .pull-right-nojs { justify-content: flex-end; }

Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - LPDDR4X
Memory Size:	16 Gbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	2.133 GHz
Package/Case:	FBGA-200
Organisation:	1 G x 16
Access Time:	10 ns
Supply Voltage - Min:	1.7 V
Supply Voltage - Max:	1.95 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 95 C
Packaging:	Tray
Brand:	Alliance Memory
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	120
Subcategory:	Memory & Data Storage

Products found:

To show similar products, select at least one checkbox

Select at least one checkbox above to show similar products in this category.

Attributes selected: 0

Filter Document:

Datasheet

AS4C1G16MD4V-046BIN Datasheet (PDF)

EOL

Product Discontinuation Notification 2026-7-17 (PDF)

Compliance Codes

CAHTS:: 8542320020
USHTS:: 8542320036
MXHTS:: 8542320299
ECCN:: EAR99

Origin Classifications

Country of Origin:: Korea, Republic of
Assembly Country of Origin:: Korea, Republic of
Country of Diffusion:: Korea, Republic of

The country is subject to change at the time of shipment.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface that transfers two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Alliance Memory DDR3L SDRAM is available in various package sizes.