Analog Devices Inc. ADSP-SC598 Dual-SHARC+® Digital Signal Processors

Analog Devices ADSP-SC598 Dual-SHARC+® Digital Signal Processors (DSPs) feature an integrated Arm® Cortex-A55 running up to 1.2GHz. The A55 processor, with FPU and Neon® DSP extensions, handles additional real-time processing tasks and manages peripherals used to interface to time-critical data in audio applications. These interfaces include Gigabit Ethernet, USB High-Speed, CAN FD, and various other connectivity options for a flexible and simplified system design.

The ADSP-SC598 SHARC processors feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high-performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). The SHARC+ core includes cache enhancements and branch prediction, while maintaining instruction set compatibility with previous SHARC products.

By integrating a rich set of industry-leading system peripherals and memory, the SHARC+ processor is the platform of choice for applications that require programmability similar to Reduced Instruction Set Computing (RISC), multimedia support, and leading-edge signal processing in one integrated package. These applications include automotive, professional audio, and industrial-based applications that require high floating-point performance.

Features

SHARC+ core infrastructure
- 800MHz (maximum) or 1GHz (maximum) core clock frequency
- 2x 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance
- 32-bit, 40-bit, and 64-bit floating point support
- 32-bit fixed point
- Byte, short-word, word, and long-word addressed
Powerful DMA system
16-bit DDR/DDR3L memory controller, 1.35V support for DDR3L
Memory
- 2048KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates the need for external memory in many use cases
- Level 3 (L3) interface optimized for low system power, providing a 16-bit interface to DDR3 (supporting 1.35V capable DDR3L devices)
Advanced hardware accelerators
- Enhanced FIR/IIR offload engines running at the core clock frequency for added processing power
- Security crypto engines with OTP
Digital Audio Interface (DAI)
- 8x full SPORT interfaces with TDM and I²S modes
- 2x S/PDIF Rx/Tx, 8x ASRC pairs
- 8x precision clock generators
- 2x 4-channel PDM mic inputs
- 40x buffers

Arm core infrastructure
- 1.2GHz Arm Cortex-A55 (with Neon/FPU)
- 32kByte/32kByte L1 instr./data cache
- 256kByte L2 cache
Other peripheral connectivity/interfaces
- 1x eMSI (SDIO/eMMC)
- 2x quad SPI, 1x octal SPI
- MLB 3-pin/6-pin
- 6x I²C, 3x UARTs
- 2x link ports
- 16x general-purpose timer, 1x general-purpose counter
- 3x watchdog timers
- ePPI
- USB 2.0 HS OTG controller
- 10/100 EMAC
- 10/100/1000 EMAC with AVB and 1588
- 2x CAN FD
- 8-ch 12-bit housekeeping ADC
- 135x GPIO pins, 40x DAI pins
- Thermal sensor
17mm x 17mm (0.8mm pitch) 400-ball CSP_BGA package
Security and Protection
- Crypto hardware accelerators
- Fast secure boot with IP protection
Enhanced FIR and IIR accelerators running up to 1GHz
AEC-Q100 qualified for automotive applications