ISSI IS67WVH/IS67WVO Memory Devices
ISSI IS67WVH/IS67WVO Memory Devices contain 64Mb/128Mb Pseudo Static Random Access (PSRAM) memory using a self-refresh DRAM array organized as 8M/16M words by 8bits. These memory devices offer up to 400MB/s of high-performance. The IS67WVH HyperRAM™ devices support a HyperBus interface, very low signal count (address, command, and data through 8 DQ pins), and hidden refresh operation. These integrated memory devices feature sequential burst transactions, Read-Write Data Strobe (RWDS), and Double Data Rate (DDR). The IS67WVO memory devices support an Octal Peripheral Interface (OPI) (address, command, and data through 8 SIO pins), very low signal count, and hidden refresh operation. These memory devices are ideal for automotive applications.Features
- IS67WVH:
- HyperBus™ low signal count interface:
- Read-Write Data Strobe (RWDS):
- Bidirectional data strobe/mask
- Output at the start of all transactions to indicate refresh latency
- Output during read transactions as read data strobe
- Input during write transactions as write data mask
- RWDS DCARS timing:
- During read transactions, RWDS is offset by a second clock, phase-shifted from CK
- Phase-shifted clock is used to move the RWDS transition edge within the read data eye
- Read-Write Data Strobe (RWDS):
- High-performance:
- Double Data Rate (DDR)
- 200MHz clock rate (400MB/s) at 105°C
- 166MHz clock rate (332MB/s) at 125°C
- Sequential burst transactions
- Configurable burst:
- Wrapped burst lengths:
- 16 bytes (8 clocks)
- 32 bytes (16 clocks)
- 64 bytes (32 clocks)
- 128 bytes (64 clocks)
- Wrapped burst lengths:
- Linear burst
- Configurable output drive strength
- HyperBus™ low signal count interface:
- IS67WVO:
- Industry standard serial interface:
- Octal Peripheral Interface (OPI) protocol
- 11 signal pins (CS#, SCLK, DQSM, and SIO0-SIO7)
- High-performance:
- Up to 400MB/s
- Double Transfer Rate (DTR) operation
- 200MHz (400MB/s)
- Source synchronous output signal during read operation (DQSM)
- Data mask during write operation (DQSM)
- Supports variable latency mode and fixed latency mode
- Supports wrapped burst mode and continuous burst mode
- Industry standard serial interface:
IS67WVO Block Diagram
IS67WVH Block Diagram
Published: 2025-06-02
| Updated: 2025-06-26
