Lattice Semiconductor CertusPro™-NX General-Purpose Low-Power FPGAs
Lattice Semiconductor CertusPro™-NX General-Purpose Low-Power FPGAs feature up to eight SERDES lanes supporting up to 10.3Gbps per lane in packages ranging from 9mm2 to 27mm2. The CertusPro-NX FPGAs offer up to 7.3Mb of on-chip memory with LPDDR4 support. Due to a low Soft Error Rate (SER) from 28nm FD-SOI technology, the Lattice Nexus platform devices provide class-leading power efficiency and high reliability. Design security includes ECDSA bitstream authentication coupled with robust AES-256 encryption. The Lattice Semiconductor CertusPro-NX General-Purpose Low-Power FPGAs are available in commercial, industrial, and automotive (AEC-Q100 qualified) temperature grades.
Features
- Programmable architecture
- 50k to 100k logic cells
- 96x to 156x multipliers (18 × 18) in sysDSP™ blocks
- 3.8Mb to 7.3Mb of embedded memory (including EBR and LRAM)
- 170x to 299x programmable sysI/O (high performance and wide range I/O)
- Programmable sysI/O designed to support a wide variety of interfaces
- High Performance (HP) I/O supported on bottom I/O banks
- Supports up to 1.8V VCCIO
- Mixed voltage support (1.0V, 1.2V, 1.5V, and 1.8V)
- High-speed differential up to 1.5Gbps
- Supports LVDS, Soft D-PHY Transmitter (Tx)/Receiver (Rx), LVDS 7:1 Tx/Rx, SLVS Tx/Rx, subLVDS Rx
- Supports SGMII (Gb Ethernet)
- 2x channels (Tx/Rx) at 1.25Gbps
- Dedicated DDR3/DDR3L and LPDDR2/LPDDR4 memory support with DQS logic, up to 1066Mbps data rate and ×64bit data width
- Wide Range (WR) I/O supported on left, right, and top I/O banks
- Supports up to 3.3V VCCIO
- Mixed voltage support (1.2V, 1.5V, 1.8V, 2.5V, and 3.3V)
- Programmable slew rate (slow, medium, and fast)
- Controlled impedance mode
- Emulated LVDS support
- Hot Socketing support
- High Performance (HP) I/O supported on bottom I/O banks
- Embedded SerDes
- From 625Mbps up to 10.3125Gbps per channel, with up to 8x channels
- Multiple Protocol PCS support
- PCIe hard IP supports
- Gen1, Gen2, and Gen3
- Endpoint and Root complex
- Multi-function up to 4x functions
- Up to 4x lanes
- Ethernet
- 10GBASE-R at 10.3125Gbps
- SGMII at 1.25Gbps and 2.5Gbps
- XAUI at 3.125Gbps per lane
- SLVS-EC at 1.25Gbps, 2.5Gbps, and 5Gbps
- DP/eDP at 1.62Gbps (RBR), 2.7Gbps (HBR), 5.4Gbps (HBR2), and 8.1Gbps (HBR3)
- CoaXPress at 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, and 6.25Gbps
- Generic 8b10b at multiple data rates
- SerDes-only mode allows direct 8-bit or 10-bit interface to FPGA logic
- Low Power and High-Performance modes
- User selectable
- Low Power mode for power saving and/or thermal challenges
- High-Performance mode for faster processing
- Small footprint package options, 9mm x 9mm to 27mm x 27mm package sizes
- 2x channels of Clock Data Recovery (CDR) up to 1.25Gbps to support SGMII on HP I/O
- CDR for Rx
- 8b/10b decoding
- Independent Loss of Lock (LOL) detector for each CDR block
- sysCLOCK™ analog PLLs
- 3x in 50k LC, and 4x in 100k LC
- 6x outputs per PLL
- Fractional N
- Programmable and dynamic phase control
- Support spread spectrum clocking
- sysDSP enhanced DSP blocks
- Hardened pre-adder
- Dynamic shift for AI/ML support
- Four 18 x 18, eight 9 x 9, two 18 x 36, or 36 x 36 multipliers
- Advanced 18 x 36, two 18 x 18, or four 8 x 8 MAC per sysDSP blocks
- Flexible memory resources
- Up to 3.7Mb sysMEM™ Embedded Block RAM (EBR) available
- Programmable width
- Error Correction Coding (ECC)
- First In First Out (FIFO)
- 344-kbits to 639-kbits distributed RAM
- Large RAM blocks
- 0.5Mbits per block
- Up to 7x (3.5Mbit total) per device
- Internal bus interface support
- APB control bus
- AHB-Lite for data bus
- AXI4-streaming
- Fast, secure configuration
- 1x, 2x, and 4x SPI up to 150MHz, Master and Slave SPI support
- JTAG
- I2C and I3C
- Ultrafast I/O configuration for instant-on support (using Early I/O Release feature)
- Less than 30ms full device configuration for the LFCPNX-100 device
- Cryptographic engine
- Bitstream encryption, using AES-256
- Bitstream authentication, using ECDSA
- Hashing algorithms, SHA and HMAC
- True Random Number Generator
- AES 128/256 encryption
- Single Event Upset (SEU) mitigation support
- Extremely low Soft Error Rate (SER) due to FD-SOI technology
- Soft Error Detect, embedded hard macro
- Soft Error Correction, transparent to user design operation
- Soft Error Injection, emulates SEU events to debug system error handling
- Dual ADC, 1MSPS, 12-bit Successive Approximation Register (SAR), with simultaneous sampling, 3x continuous-time comparators
- System-level support
- IEEE 1149.1 and IEEE 1532 compliant
- Reveal Logic Analyzer
- On-chip oscillator for device initialization and general use
- 1.0V core power supply
Applications
- Smart SFP+ and optical modules
- Control plane security and hardware management
- Machine vision
- Frame grabbers
- Smart camera AI processing
Block Diagram
Videos
Technical Notes
- ADC User Guide for Nexus Platform
- Multi-Boot User Guide for Nexus Platform
- Memory User Guide for Nexus Platform
- Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
- sysDSP User Guide for Nexus Platform
- sysCONFIG User Guide for Nexus Platform
- sysI/O User Guide for Nexus Platform
- CertusPro-NX SerDes/PCS User Guide
- CertusPro-NX High-Speed I/O Interface
- CertusPro-NX Hardware Checklist
- Using TraceID
- Minimizing System Interruption During Configuration Using TransFR Technology
- Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
- Sub-LVDS Signaling Using Lattice Devices
- Single Event Upset (SEU) Report for Nexus Platform
- Thermal Management
White Papers
Related Platform
Lattice Semiconductor Nexus Platform
Enables low power, high reliability, and high-performance design.
Board
Lattice Semiconductor CertusPro™-NX Sensor to Ethernet Bridge Board
Features the CertusPro-NX-100 FPGA & CrossLink-NX-17, which output to a host system over Ethernet.
Published: 2023-09-05
| Updated: 2025-03-24