Renesas Electronics 9DBL PCIe Zero-Delay Buffers
Renesas Electronics 9DBL PCIe Zero-Delay Buffers are 3.3V devices that support PCIe Gen1-4 Common Clocked (CC) systems. The 9DBL also supports PCIe Gen2 Separate Reference Independent Spread (SRIS) systems. The buffers provide a direct connection to 85Ω or 100Ω transmission lines with a choice of integrated output terminations. Renesas Electronics 9DBL PCIe Zero-Delay Buffers can be factory programmed with a user-defined power-up default SMBus configuration.
Features
- Direct connection to 100Ω (xx41, xx42) or 85Ω (xx51, xx52) transmission lines
- SMBus-selectable features allow optimization to customer requirements:
- Control input polarity
- Control input pull up/downs
- Slew rate for each output
- Differential output amplitude
- Output impedance for each output
- 50MHz, 100MHz, or 125MHz operating frequency
- Customer defined SMBus power up default can be programmed into P1 device; allows exact optimization to customer requirements
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- Spread Spectrum tolerant; allows reduction of EMI
- Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
- Outputs blocked until PLL is locked; clean system start-up
- Device contains default configuration; SMBus interface not required for device operation
- Three selectable SMBus addresses; multiple devices can easily share an SMBus segment
- Space-saving 24-pin 4x4mm VFQFPN; minimal board space
Applications
- Riser cards
- Storage
- Networking
- JBOD
- Communications
- Access points
Published: 2016-08-04
| Updated: 2022-10-05